Shift registers comprising a series of inverters separated by transfer gates are used in a large number of applications. When a transfer gate is made of a pair of P-channel and N-channel MOS FETs connected in parallel, clock signals .phi. and .phi. are applied to gate electrodes of the MOS FETs of the transfer gate to control the shift of information.
It is usual that the clock signal .phi. is generated by inverting the master clock signal .phi.. The inversion operation takes a short time, and after the master clock signal .phi. becomes a logic "1" or "0", there is only a short delay time before the clock signal .phi. becomes a logic "0" or "1".
Consequently the levels of clock signals .phi. and .phi. are a logic "1" or "0" substantially simultaneously, and all transfer gates become conductive. Therefore the information applied to the input of the shift register passes through to the output. This is called "race hazards" or "racing".